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  Advanced Computing and EDA (ACE) Lab at SJTU
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About the Group
The group consists of Prof. Weikang Qian and his students in the University of Michigan-Shanghai Jiao Tong University Joint Institute at Shanghai Jiao Tong University. In our research, we try to unlock the power of emerging computing paradigms such as approximate computing, stochastic computing, and in-memory computing to design advanced next-generation computing circuits and systems. An enabling approach (and our favorite!) to this is through electronic design automation (EDA). Our specific research interest includes:
  • EDA algorithms such as ogic synthesis, high-level synthesis, and standard-cell synthesis;
  • EDA and digital design for novel computing paradigms such as approximate computing, stochastic computing, and in-memory computing;
  • EDA and digital design for specific applications such as artificial intelligence, digital signal processing, and communication;
  • EDA and digital design for emerging technologies such as memristors, carbon-nanotube field effect transistors, and single-electron transistors.

We welcome you to explore this website of our group:
  • See our "People" page for a list of everyone in the group.
  • See our "Research" page for an overview of our research activities.
  • See our "Publications" page for our papers.
  • See our "Teaching" page for courses that Weikang teaches.
  • See our "Activities" page for activities that Weikang engages in.
  • See our "Codes & Links" page for some software download links.

Open Positions
We are constantly hiring graduate students and postdocs who are interested in electronic design automation (EDA), digital design, or computer architecture. However, students/postdocs with various backgrounds from Electrical Engineering, Computer Engineering, Computer Science, Automation, or Mathematics are also welcome to apply. Preference will be given to applicants with strong backgrounds in math (especially discrete math, probability and random processes, or optimization) and/or programming.

We also have positions for undergraduate students. Preference will be given to these undergraduate students who are highly-motivated and interested in joining our group for further graduate study.

If interested in any of the above positions, please send an email with a copy of your CV to Weikang at qianwk@sjtu.edu.cn.

Selected Highlights

Current Announcement
  • Highlights Our paper entitled "A recursive partition-based in-memory SIMD computation scheduler for memory footprint minimization" was accepted by the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This work is first-authored by a Ph.D. student, Xingyue Qian.

  • Highlights Our paper entitled "AccALS 2.0: Accelerating approximate logic synthesis by simultaneous selection of multiple local approximate changes" was accepted by the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This work is first-authored by a Ph.D. student, Xuan Wang.

  • Highlights Our paper entitled "Efficient resubstitution-based approximate logic synthesis" was accepted by the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This work is first-authored by a former Ph.D. student, Chang Meng.
Past Announcement
2024
 2023
  • Highlights  Our paper entitled "DASALS: Differentiable architecture search-driven approximate logic synthesis" was accepted by the the 2023 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D. student, Xuan Wang. It adopts the idea of neural architecture search and proposes a new approximate logic synthesis method.
  • Highlights  Our paper entitled "MiniTNtk: An exact synthesis-based method for minimizing transistor network" was accepted by the the 2023 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D. student, Weihua Xiao. It proposes a method to synthesize a transistor network with the fewest transistors for a given Boolean function.

  • Highlights Kuncai Zhong obtained his Ph.D. degree in June, 2023. He joined College of Semiconductors (College of Integrated Circuits), Hunan University as an assistant professor. Congratulations! (See news)

  • Highlights Chang Meng obtained his Ph.D. degree in June, 2023. He joined EPFL, Switzerland as a postdoc researcher under the supervision of Prof. Giovanni De Micheli. Congratulations!

  • Wenhui Liang and Yi Ren joined our group as Ph.D. students in September, 2023. Welcome, Wenhui and Yi!

  • Highlights  Our paper entitled "HEDALS: Highly efficient delay-driven approximate logic synthesis" was accepted by the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This work is first-authored by a Ph.D. student, Chang Meng. The code is made open source.

  • Highlights Our paper entitled "AccALS: Accelerating approximate logic synthesis by selection of multiple local approximate changes" was accepted by the 2023 Design Automation Conference. This work is first-authored by a Ph.D. student, Xuan Wang. It proposes a novel framework for accelerating iterative approximate logic synthesis flows based on simultaneous selection of multiple local approximate changes in a single round.

  • Our paper entitled "Implementing Boolean function by ternary content addressable memory with approximate match" was accepted by the 2023 China Semiconductor Technology International Conference (CSTIC). This work is first-authored by a Ph.D. student, Jian Shi.

  • Highlights Our paper entitled "High-accuracy low-power reconfigurable architectures for decomposition-based approximate lookup table" was accepted by the 2023 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a Ph.D. student, Xingyue Qian. It proposes a new and effective approximate Boolean decomposition algorithm together with two reconfigurable architectures based on approximate decomposition.

  • Highlights Our paper entitled "MECALS: A maximum error checking technique for approximate logic synthesis" was accepted by the 2023 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a Ph.D. student, Chang Meng. It proposes an efficient method for approximate logic synthesis under maximum error constraint. The code is made open source.
2022
  • Zexi Li and Ruicheng Dai joined our group as Ph.D. students in September, 2022. Welcome, Zexi and Ruicheng!

  • Our paper entitled "Scheduling information-guided efficient high-level synthesis design space exploration" was accepted by the 2022 International Conference on Computer Design (ICCD). This work is first-authored by a Ph.D. student, Xingyue Qian.

  • Highlight Our paper entitled "Exploiting uniform spatial distribution to design efficient random number source for stochastic computing" was accepted by the 2022 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D. student, Kuncai Zhong. It proposes a random number source design methodology based on uniform distribution for stochastic computing.

  • Highlight Our paper entitled "ASPPLN: Accelerated symbolic probability propagation in logic network" was accepted by the 2022 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D. student, Weihua Xiao. It proposes an efficient symbolic probability propagation method, which is useful in power estimation, reliability analysis, and error analysis for approximate circuits.

  • Shanshan Han joined our group as a Ph.D. student in April, 2022. Welcome, Shanshan!

  • Xingyue Qian successfully transferred as a Ph.D. student in our group. Congratulations, Xingyue!
  • Ziqi Meng obtained her master of science degree in March, 2022. She continued her Ph.D. study at the University of Pennsylvania. Congratulations!
  • Highlight Our paper entitled "SEALS: Sensitivity-driven efficient approximate logic synthesis" was accepted by the 2022 Design Automation Conference (DAC). This work is co-first-authored by two Ph.D. students, Chang Meng and Xuan Wang. It proposes a sensitivity-driven efficient approximate logic synthesis (ALS) method to speed up a greedy ALS flow. SEALS centers around a novel concept called sensitivity, which enables a fast and accurate error estimation method and an efficient method to filter out unpromising local approximate changes.
  • Highlight Our paper entitled "Write or not: Programming scheme optimization for RRAM-based neuromorphic computing" was accepted by the 2022 Design Automation Conference (DAC). This work is first-authored by a master student, Ziqi Meng. It optimizes the write-and-verify process used to tolerate the device-to-device variation and the cycle-to-cycle variation of RRAM devices used in neuromorphic computing. Specifically, it proposes a probabilistic termination criterion on a single device and a systematic optimization method on multiple devices.

  • Our paper entitled "MinAC: Minimal-area approximate compressor design based on exact synthesis for approximate multipliers" was accepted by the 2022 IEEE International Symposium on Circuits and Systems (ISCAS). This work is first-authored by a Ph.D. student, Xuan Wang. The code is made open source.

  • Our paper entitled "Quantified satisfiability-based simultaneous selection of multiple local approximate changes under maximum error bound" was accepted by the 2022 IEEE International Symposium on Circuits and Systems (ISCAS). This work is first-authored by an undergraduate student, Chenfei Lou.

  • HighlightOur paper entitled "Towards low-cost high-accuracy stochastic computing architecture for univariate functions: Design and design space exploration" was accepted by the 2022 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a Ph.D. student, Kuncai Zhong. It proposes a stochastic computing architecture with a single stochastic number generator and a minimum number of D flip-flops to implement univariate functions. To efficiently configure the architecture to achieve a high accuracy, a design space exploration method is also proposed.

  • Highlight Our paper entitled "OPACT: Optimization of approximate compressor tree for approximate multiplier" was accepted by the 2022 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a Ph.D. student, Weihua Xiao. It proposes a method for optimizing approximate compressor tree of approximate multiplier. The method includes two parts, optimization of compressor allocation and optimization of connection order of the compressors.

  • Highlight Our paper entitled "VECBEE: A versatile efficiency-accuracy configurable batch error estimation method for greedy approximate logic synthesis" was accepted by the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. This work is co-first-authored by a previous master student, Sanbao Su, and a current Ph.D. student, Chang Meng. The code is made open source.
2021
  • Jian Shi and Xianjue Cai joined our group as Ph.D. students in September, 2021. Welcome, Jian and Xianjue!

  • Chen Wang obtained his Ph.D. degree in September, 2021. He joined Shanghai AnLogic Infotech Co., Ltd. Congratulations!
  • Highlights Our paper entitled "DALTA: A decomposition-based approximate lookup table architecture" was accepted by the 2021 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D. student, Chang Meng. It proposes a low-cost reconfigurable lookup table architecture based on Boolean decomposition to implement target functions approximately, together with the associated configuration methods.

  • Highlights Our paper entitled "MinSC: An exact synthesis-based method for minimal area stochastic circuits under relaxed error bound" was accepted by the 2021 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D. student, Xuan Wang. It proposes an SMT-based exact synthesis method for obtaining an area-optimal stochastic circuits under relaxed error bound. The code is made open source.

  • We are invited to present our work entitled "Approximate logic synthesis in the loop for designing low-power neural network accelerator" at the 2021 International Symposium on Circuits and Systems (ISCAS). This work is first-authored by an undergraduate student, Yifan Qian.

  • Highlights Our paper entitled "GOMIL: global optimization of multiplier by integer linear programming" was accepted as an oral presentation by the 2021 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a Ph.D. student, Weihua Xiao. It proposes an effective integer linear programming-based method for global optimization of digital multipliers. The code is made open source.

  • Highlights Our paper entitled "Digital offset for RRAM-based neuromorphic computing: a novel solution to conquer cycle-to-cycle variation" was accepted as an oral presentation by the 2021 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a master student, Ziqi Meng. It proposes an effective solution for addressing the resistance variation problem of RRAM crossbar-based neural network accelerators. The idea is to introduce tunable digital offsets into the RRAM crossbar, which enables a variation-aware weight optimization and a post-writing tuning technique. 
2020
  • Xingyue Qian joined our group as a master student in September, 2020. Welcome, Xingyue!

  • Xuan Wang joined our group as a Ph.D. student in August, 2020. Welcome, Xuan!

  • Highlights Our paper entitled "Exploring target function approximation for stochastic circuit minimization" was accepted by the 2020 International Conference on Computer-Aided Design (ICCAD). This work is first-authored by a Ph.D student, Chen Wang. It proposes a method that explores target function approximation to derive an SC circuit with significantly reduced area and delay. The code is made open source.

  • Highlights A collaborated paper entitled "Optimally approximated and unbiased floating-point multiplier with runtime configurability" was accepted by the 2020 International Conference on Computer-Aided Design (ICCAD) and nominated for the best paper award.

  • Highlights Our paper entitled "ALSRAC: approximate logic synthesis by resubstitution with approximate care set" was accepted by the 2020 Design Automation Conference (DAC). This work is first-authored by a Ph.D student, Chang Meng. It proposes an efficient and effective approximate logic synthesis flow based approximate resubstitution. The code is made open source.
  • Highlights Our paper entitled "When sorting network meets parallel bitstreams: A fault-tolerant parallel ternary neural network (TNN) accelerator based on stochastic computing" was accepted as a poster presentation by the 2020 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by Yawen Zhang, a co-advised student. It gives a novel view on parallel bit stream computing.

  • Highlights Our paper entitled "Go unary: a novel synapse coding and mapping scheme for reliable ReRAM-based neuromorphic computing" was accepted as a long presentation by the 2020 Design, Automation, and Test in Europe Conference (DATE) and nominated for the best paper award. This work is first-authored by Chang Ma, a co-advised student. It applies unary encoding, an encoding form related to stochastic encoding, to solve the reliability issue of ReRAM-based crossbar array for performing matrix-vector multiplication operation.

  • Highlights Our paper entitled "Accuracy analysis for stochastic circuits with D-flip flop insertion" was accepted as a long presentation by the 2020 Design, Automation, and Test in Europe Conference (DATE). This work is first-authored by a Ph.D. student, Kuncai Zhong.
2019
 2018
  • Highlights Weikang recieved the 2018 Research Excellence Award at JI.
  • Our paper on two-level approximate logic synthesis was accepted by IEEE Transactions on Computer Aided-Design of Integrated Circuits and Systems. This work is first-authored by a master student, Sanbao Su.

  • Highlights Zhuangzhuang Zhou, a JI undergraduate student, was awarded the first place at the ACM Special Interest Group on Design Automation Student Research Competition (ACM/SIGDA SRC) - undergraduate student category. Congratulations to Zhuangzhuang!
  • Kuncai Zhong and Chang Meng joined our group as Ph.D. students in September, 2018. Welcome, Kuncai and Chang!

  • Highlights We presented our work on delay-driven approximate logic synthesis at the 2018 International Conference on Computer-Aided Design (ICCAD) in Nov., 2018. This work is first-authored by a JI undergraduate student, Zhuangzhuang Zhou.

  • Our paper on error analysis of approximate adders was accepted by IEEE Transactions on Computers. This work is co-first-authored by a Ph.D. student, Yi Wu and two JI undergraduate students, You Li and Xiangxuan Ge.

  • Our paper on synthesizing stochastic circuits was accepted by IEEE Transactions on Computer Aided-Design of Integrated Circuits and Systems. This work is first-authored by a JI undergraduate student, Zhijing Li.

  • Highlights We presented our work on error estimation for approximate logic synthesis at the 2018 Design Automation Conference (DAC) in June, 2018. This work is first-authored by a master student, Sanbao Su.
2017
 2016
 2015
 2014
  • Highlights We presented our work on synthesizing stochastic computing circuits at the International Conference on Computer-Aided Design in November, 2014. This work is first-authored by a JI undergraduate student, Yili Ding.

  • Highlights We presented our work on synthesizing single-electron transistor circuits at the International Conference on Computer-Aided Design in November, 2014. This work is first-authored by a master student, Zheng Zhao.

  • Zili Lin and Xuesong Peng joined our group as master students in September, 2014. Welcome, Zili and Xuesong!

  • We received a general-program grant from National Natural Science Foundation of China (jointly with Prof. Bo Yuan from CS Department at SJTU) to study how to design stochastic computing circuits and architectures for machine learning and inference applications.

  • We received a grant from Capital Microelectronics Corporation to study how to accelerate FPGA technology mapping using multicore processors.

  • Chen Wang obtained his master of science degree in March, 2014. Congratulations! Chen will continue for a Ph.D. study in our group.
2013
  • Chuyu Shen joined our group as master students in September, 2013. Welcome, Chuyu!

  • We presented our work on synthesizing stochastic computing circuits at the International Symposium on Circuits and Systems in May, 2013. This work is first-authored by a JI undergraduate student, Daran Cai.

  • We presented our work on synthesizing combinational logic to generate probabilities at the Asia and South Pacific Design Automation Conference in January, 2013. This work is first-authored by a master student, Chen Wang.

2012