- HEDALS: Highly efficient
delay-driven approximate logic synthesis (IEEE
TCAD'23): Paper;
Source
Code
- MECALS: A maximum error checking
technique for approximate logic synthesis (DATE'23):
Paper;
Source
Code
- VECBEE: A versatile
efficiency-accuracy configurable batch error
estimation method for greedy approximate logic
synthesis (IEEE TCAD'22): Paper;
Source
Code
- MinAC: Minimal-area approximate
compressor design based on exact synthesis for
approximate multipliers (ISCAS'22): Paper;
Source
Code
- MinSC: An exact synthesis-based
method for minimal-area stochastic circuits under
relaxed error bound (ICCAD'21): Paper;
Source
Code
- GOMIL: global optimization of
multiplier by integer linear programming (DATE'21):
Paper;
Source
Code
- Exploring target function
approximation for stochastic circuit minimization
(ICCAD'20): Paper;
Source
Code
- ALSRAC: Approximate logic synthesis
by resubstitution with approximate care set
(DAC'20): Paper;
Source
Code
- DALS: Delay-driven approximate logic
synthesis (ICCAD'18): Paper;
Source
Code
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