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Emerging Computing Technology Laboratory at SJTU |
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| Approximate Computing |
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Three important goals
of VLSI design are reducing circuit area, improving
circuit frequency, and reducing power consumption, all
of which are achieved under the basic assumption that
the circuit correctly implements the specified
function. However, many applications widely used
today, such as signal processing, pattern recognition,
and machine learning, do not require perfect
computation. Instead, results with small errors are
still acceptable. A new design paradigm, known as approximate
computing, is recently proposed to
design circuits for those error-tolerant applications.
Exploiting the error tolerance of applications, it
deliberately sacrifices a small amount of accuracy to
achieve improvement in area, performance, and power
consumption.
An example of
approximate computing is shown in Fig. 1. Fig. 1(a)
shows the Karnaugh map of an accurate 2-bit
multiplier. If we change the output "1001" in the red
circle in Fig. 1(a) to "111", we obtain the Karnaugh
map of an approximate 2-bit multiplier, as shown in
Fig. 1(b). The circuit for the accurate multiplier and
that for the approximate multiplier are shown in Fig.
1(c) and 1(d), respectively. Notice that by
introducing a small amount of inaccuracy, we reduce
both the area and the delay of the original multiplier
significantly.
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| Selected Publications on Approximate Logic Synthesis |
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| Selected Publications on the Design, Synthesis, and Analysis of Approximate Arithmetic Circuits |
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| Selected Publications on the Design of Approximate Computing Architectures |
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| Stochastic Computing |
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Traditional
arithmetic circuits operate on numbers encoded by
binary radix, which is a deterministic way to
represent numerical values with zeros and ones.
Fundamentally different from the binary radix,
stochastic encoding is another way to represent
numerical values by logical zeros and ones. In
such a encoding, a real value p in the unit
interval is represented by a sequence of N random
bits X1, X2, ..., XN,
with each Xi having
probability p of being one and probability (1-p)
of being zero, i.e., P(Xi
= 1) = p and P(Xi
= 0) = 1-p. Fig.
2(a) shows an example of a stochastic bit stream
encoding the value 5/8.
Since the random
sequences are composed of binary digits, we can apply
digital circuits to process them. Thus, instead of
mapping Boolean values into Boolean values, a digital
circuit now maps real probability values into real
probability values. We refer to this type of
computation as stochastic
computing. Fig. 2(b) illustrates an AND gate
performing multiplication on stochastic bit streams.
We study the following fundamental problems related to stochastic computing:
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| Selected Publications on the Synthesis of Stochastic Computing Circuits |
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| Selected Publications on the Generation of Stochastic Bit Streams |
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| Selected Publications on Architectures and Applications of Stochastic Computing |
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| Deep Neural Network Accelerators |
| Deep neural networks (DNNs) have achieved a
great success in the past decade due to their high
accuracy and have been successfully applied in many
domains including computer vision and speech
recognition. However, they involve many
multiply-and-accumulate (MAC) operations, which makes
the traditional Von Neumann architecture unsuitable. To
address this challenge, novel DNN accelerators are being
actively explored. We study how to apply stochastic
computing and approximate computing to design
energy-efficient DNN accelerators. In this case, both
computing paradigms allow efficient design of
multipliers and adders, while their computational
accuracy loss is well tolerated by the DNN application.
We also study how to design DNN accelerators using
emerging devices. One particular device we are
interested in is resistive
random access memory (ReRAM). ReRAM-based crossbars
can naturally implement matrix-vector multiplication.
However, they have notorious reliability issues. We
study how to design reliable DNN accelerators using
ReRAM-based crossbars. |
| Selected Publications |
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| Design Automation for Emerging
Technologies |
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As
CMOS technology is scaled into the nanometer regime,
power consumption has become one of the
paramount concerns in designing very large scale
integrated (VLSI) circuits. To address this challenge,
alternatives to CMOS technology are being actively
explored. We are exploring two kinds of promising
substitutes for CMOS devices and addressing challenges
in designing VLSI circuits with them:
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| Selected Publications |
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